In SIP which did the stack of the two semiconductor chips, module terminals, such as a ball grid array (BGA), are arranged in the back surface of a module substrate. On the surface of a module substrate, the bonding lead combined with a module terminal is formed. The corresponding electrode pad of two semiconductor chips by which the stack was done is connected to a bonding lead with a wire. When many electrode pads are arranged along the side of the same side of both semiconductor chips, the bonding leads to which they are connected are arranged along one side of a module substrate at two rows in front and back. For example, the bonding lead of the front row is connected to the electrode pad of the semiconductor chip arranged downward with a wire, and the bonding lead in the back row is connected to the electrode pad of the semiconductor chip arranged upwards with a wire. In Patent Reference 1, as such a configuration of connection, since it is a problem that the wire contacts a semiconductor chip and other wires, when connecting the electrode pad of an upper semiconductor chip to a corresponding bonding lead directly, and the connection wire becomes long, the structure that a relay terminal is formed in a lower semiconductor chip, a wire was connected to the relay terminal from the electrode pad of the upper semiconductor chip, and the wire was connected to the corresponding bonding lead from the relay terminal is shown as a connection with the corresponding bonding lead from the electrode pad of the upper semiconductor chip. Especially in Patent Reference 1, since the size of the semiconductor chip which is stacked upward is restricted with the structure which arranges a relay terminal to both sides of the lower semiconductor chip by which the stack was done, the structure which loses one relay terminal, makes it deflect to the side which lost the relay terminal, and does the stack of another semiconductor chip on it is proposed. By bringing the upper semiconductor chip close to the border portion of a lower semiconductor chip, and deflecting it, the wire which connects the electrode pad of the upper semiconductor chip to the bonding lead of the module substrate can be made short to the degree which can link directly at the side brought close. As a result, it is supposed that a relay terminal can be excluded from the one-side side of the semiconductor chip which is stacked downward, and the miniaturization of the semiconductor chip which is stacked downward is realizable.
[Patent Reference 1] Japanese Unexamined Patent Publication No. 2002-43503